This section provides background information and introduces information related to various aspects of the disclosures that are described and/or claimed below. These background statements are not admissions of prior art.
The majority of chip manufacturing takes advantage of silicon processing on high-quality, large-area, low-cost silicon wafers. Commercial manufacturers of devices made from compound semiconductors such as gallium arsenide and indium phosphide generally have been unable to take advantage of silicon wafers. They typically build light emitting diodes (LEDs), multi junction solar cells, and other compound semiconductor devices on small, expensive wafers made of materials such as sapphire, germanium, gallium arsenide, or silicon carbide.
The challenge of making compound semiconductor devices on inexpensive substrates has widespread economic implications. Compound semiconductors are an important component of our communications infrastructure because they can emit and detect light. They are the materials in the lasers that transmit signals through optical fibers, the sensors that receive those signals, the amplifiers in cellular telephones, the amplifiers in cell phone base stations, and the circuits that transmit and receive microwave signals.
Light emitting diodes typically consist of gallium nitride films deposited onto sapphire or silicon carbide wafers. These exotic substrates contribute to the high cost of LEDs. A sapphire wafer 4 inches in diameter typically costs around $130, and a 2-inch silicon carbide wafer can cost about $2000. By contrast, an 8-inch silicon wafer, which provides four times as much surface area as a 4-inch wafer and 16 times as much surface area as a 2-inch wafer, typically costs less than $100.
High-efficiency multi junction solar cells typically contain layers of germanium, gallium arsenide, and indium gallium phosphide deposited onto germanium wafers. As is the case with wafers for LEDs, germanium wafers similarly are smaller and significantly more expensive than silicon wafers.
The ability to create compound semiconductor devices on silicon wafers facilitates market growth in several key industries.
Two key technical barriers have prevented the fabrication of compound semiconductor devices on silicon wafers: the mismatch of lattice constants and the mismatch of thermal expansion coefficients.
Lattice Mismatch:
In a crystal, the atoms sit in a regular periodic array known as a lattice. The distance between the atoms, known as the “lattice constant,” is typically a few angstroms (1 angstrom=10−10 meter). Silicon has a smaller lattice constant than many compound semiconductors. When compound semiconductors grow on silicon, crystalline imperfections known as misfit dislocations appear at the interface. The misfit dislocations create other crystalline defects known as threading dislocations, which propagate upward from the interface. Threading dislocations diminish the performance and the reliability of compound semiconductor devices such as lasers, solar cells, light-emitting diodes, etc.
Thermal Contraction Mismatch:
Compound semiconductors typically grow at high temperatures, which can exceed 1000° C. When the wafer cools, the compound semiconductor film may contract more than the silicon wafer. As a result, the wafer may bow in a concave manner, stressing and ultimately cracking the film.
Until recently, the most promising previous efforts to grow high-quality compound semiconductors onto silicon substrates have relied on three approaches: graded buffer layers, wafer bonding, or selective growth on mesas. None of these approaches has achieved commercial success.
In graded buffer layers, the composition of the material changes gradually from substantially pure silicon to a pure compound semiconductor. Since the lattice constant also changes gradually, crystalline defects are less likely to form at the interface. Unfortunately, the graded buffer layers have to be relatively thick (about ten microns for a 4% lattice mismatch). The thick buffer layer increases both the costs and the likelihood of cracking.
Wafer bonding involves growing devices on expensive substrates, then lifting off the devices and bonding them to a silicon wafer. This approach rules out modem silicon processing as a route to cost reduction. Furthermore, bonding typically requires temperatures above 300° C. When the materials cool, the compound semiconductors may crack because they contract more than the silicon wafer.
Selective growth on a mesa exploits the mobility of some dislocations. The strategy is to deposit compound semiconductors in small regions (10 to 100 microns in length), thereby providing a short path where mobile dislocations can glide to the edge of the region and remove themselves from the device. However, structures created by this technique typically have a high density of threading dislocations (more than 100 million per square centimeter). This technique cannot remove immobile dislocations, which predominate when the lattice mismatch exceeds 2%.
Aspect Ratio Trapping (J. S. Park et al., APL 90, 052113 (2007), hereby incorporated by reference in its entirety) is a recently developed technology that makes it possible to deposit high quality compound semiconductors, germanium or other lattice mismatched materials on silicon wafers. FIG. 1 illustrates the principle of Aspect Ratio Trapping (ART). A thin film of dielectric material 20 such as silicon dioxide (SiO2) or silicon nitride (SiNx) is deposited onto a silicon wafer 10. Those of skill in the art can select a variety of dielectric materials such as SiOxNy, and silicates or oxides of material such as Hf and Zr, such as HfO.
A trench is etched in the dielectric material, and then deposit a non-lattice-matched semiconductor 30 such as germanium or a compound semiconductor in the trench. The threading dislocations 40, shown as dotted lines, propagate upward, typically at approximately a 45 degree angle from the interface, then intersect the sidewalls of the trench, where they terminate. Threading dislocations 40 cannot propagate down the length of the trench because crystal facets guide them to the sidewalls. Reference is made to the region in the trench where the sidewalls trap threading dislocations as the “trapping region” 50. The upper region of the non-lattice-matched semiconductor 30, above the trapping region 50, is a relatively defect-free region 60.
ART addresses the issue of cracking caused from mismatch of thermal expansion coefficients for these reasons: (1) the stresses are small because the epitaxial layers are thin; (2) the material can elastically accommodate the stresses arising from thermal expansion mismatch because dimensions of the ART openings are small; and (3) the SiO2 pedestals, which are more compliant than the semiconductor materials, may deform to accommodate the stress.